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ics for communications quad isdn high voltage power controller qihpc peb/f 2426 version 1.1 preliminary data sheet 06.99 ds 1
? for questions on technology, delivery and prices please contact the infineon technologies offices in germany or the infineon technologies companies and representatives worldwide: see our webpage at http://www.infineon.com ? peb/f 2426 revision history: current version: 06.99 previous version: none page (in previous version) page (in current version) subjects (major changes since last revision) edition 06.99 published by infineon technologies ag i. gr., sc, balanstra?e 73, 81541 mnchen ? infineon technologies ag i.gr. 14/6/99. all rights reserved. attention please! as far as patents or other rights of third parties are concerned, liability is only assumed for components, not for applications, processes and circuits implemented within components or assemblies. the information describes the type of component and shall not be considered as assured characteristics. terms of delivery and rights to change design reserved. due to technical requirements components may contain dangerous substances. for information on the types in question please contact your nearest infineon technologies office. infineon technologies ag is an approved cecc manufacturer. packing please use the recycling operators known to you. we can also help you C get in touch with your nearest sales office. by agreement we will take packing material back, if it is sorted. you must bear the costs of transport. for packing material that is returned to us unsorted or which we are not obliged to accept, we shall have to invoice you for any costs incurred. components used in life-support devices or systems must be expressly authorized for such purpose! critical components 1 of the infineon technologies ag, may only be used in life-support devices or systems 2 with the express written approval of the infineon technologies ag. 1 a critical component is a component used in a life-support device or system whose failure can reasonably be expected to cause the failure of that life-support device or system, or to affect its safety or effectiveness of that device or system. 2 life support devices or systems are intended (a) to be implanted in the human body, or (b) to support and/or maintain and sustain human life. if they fail, it is reasonable to assume that the health of the user may be en- dangered. abm ? , aop ? , arcofi ? , arcofi ? -ba, arcofi ? -sp, digitape ? , epic ? -1, epic ? -s, elic ? , falc ? 54, falc ? 56, falc ? -e1, falc ? -lh, idec ? , iom ? , iom ? -1, iom ? -2, ipat ? -2, isac ? -p, isac ? -s, isac ? -s te, isac ? -p te, itac ? , iwe ? , musac ? -a, octat ? -p, quat ? -s, sicat ? , sicofi ? , sicofi ? -2, sicofi ? -4, sicofi ? -4c, slicofi ? are registered trademarks of infineon technologies ag. ace ? , asm ? , asp ? , potswire ? , quadfalc ? , scout ? are trademarks of infineon technologies ag.
peb 2426 pef 2426 table of contents page preliminary data sheet 3 06.99 1 overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .6 1.1 features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .7 1.2 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 1.3 typical applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 2 pin descriptions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.1 pin configuration (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 2.2 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .12 3 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.1 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 3.2 biasing circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 3.3 line feed control circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 3.4 line current control circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 3.5 relays driver circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 4 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.1 resistor rs1..4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.2 resistor rf . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.3 capacitor cs1..4 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 4.4 protection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 5 operational description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 6 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 6.1 absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 6.2 ac/dc-characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 6.3 operating range . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 6.4 static thermal resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 6.5 testing the electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 7 package outlines . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30
peb 2426 pef 2426 list of tables page preliminary data sheet 4 06.99 table 1 pin definitions and functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2 thermal detector threshold levels . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 3 function table for controlling one line . . . . . . . . . . . . . . . . . . . . . . . 17 table 4 dc characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
peb 2426 pef 2426 list of figures page preliminary data sheet 5 06.99 figure 1 logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .8 figure 2 16-line card application with delphi and quad-u . . . . . . . . . . . . . . .9 figure 3 system integration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .10 figure 4 pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .11 figure 5 functional block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .14 figure 6 delay time toc as a function of the value of cs1..4 (typical values). . .19 figure 7 proposal for a protection circuitry . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 figure 8 circuit with lt power source test loads . . . . . . . . . . . . . . . . . . . . . .21 figure 9 simultaneous power up sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 figure 10 supply currents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .26 figure 11 line currents and delay time toc . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 12 dmos-ron resistance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 figure 13 pf1..4, logic input levels and nack1..4, logic output levels . . . . . .28 figure 14 rdin1..8, relay driver inputs and rdout1..8 relay driver outputs . . .29 figure 15 test circuit for maximum dc-voltages, pulse voltages and impulse voltag- es on pins d1..429
peb 2426 pef 2426 preliminary data sheet 6 06.99 1 overview the quad isdn high voltage power controller provides a power source for up to four u-line interfaces. the power source to the device is a local battery or a centralized power supply. each powered line is individually controlled and monitored by the device interface. line powering can be switched on or off by command. the qihpc indicates, when the output current is above a threshold for longer than the programmable time t oc . at a second (higher) value the current is limited. the values of the current limitation and the overcurrent indication threshold are defined with external resistors, the overcurrent indication setup delay is selected by external capacitances. the status information of each line (acknowledge of requested power feed) is returned to the system. the status information enables an easy detection of overloads and faults and a fast localization even on a large system. the integrated intelligent chip temperature control guards the qihpc in case of overloads. additionally eight drivers for external relays and their control logic are integrated on the qihpc. these relay drivers provide open collector output stages with high current capability.
p-mqfp-44 preliminary data sheet 7 06.99 quad isdn high voltage power controller qihpc peb 2426 version 1.1 spt 170 type package peb 2426 p-mqfp-44 1.1 features ? isdn line feed supply voltage up to 130 v ? supplies power for up to four isdn transmission lines ? etsi ts 102 080 compatible ? separate current monitoring and limiting for each line ? current limiting level can be programmed by an external resistor ? overcurrent indication threshold can be programmed with external resistors independently from the current limitation. ? the overcurrent indication setup delay can be programmed by external capacitors, separately for each line ? intelligent chip temperature control ? automatically switching off lines in current limitation when expecting over temperature problems ? automatically switching off all four lines in case of real overtemperature ? integrated relay drivers and relay driver controlling for eight relays ? optimized for working in conjunction with peb 24901 (dfe-t), peb 24911 (dfe-q), and peb 2491 (quad-u) ? small p-mqfp-44 package ? reliable 170 v smart power technology
peb 2426 pef 2426 preliminary data sheet 8 06.99 1.2 logic symbol ? figure 1 logic symbol v ilf s 1 . . . s 4 c s1 . . . c s4 rd in1 . . . rd in8 rd out1 . . . rd out8 qihpc rf pos rf neg relay driver input pins relay driver pins power feed control pins power feed status pins nack 1 nack 2 nack 3 nack 4 pf 2 pf 1 pf 4 pf 3 power feed d 2 d 4 d 1 d 3 battery voltage current sensing capacitor low pass filter current sensing v dd gnd
peb 2426 pef 2426 preliminary data sheet 9 06.99 1.3 typical applications the qihpc is an integrated power controller especially designed for feeding two-wire isdn-transmission lines. four u interface lines can be powered by one qihpc. figure 2 16-line card application with delphi and quad-u figure 3 gives general overview of the system integration of the qihpc. because of integrated pull-down current-sinks on the input pins pf 1..4 and rd in1..8 only connections to v dd are necessary to switch on power feeding to the lines or to switch on the relay drivers. when power feeding to a line is switched on, and this line is in a normal feeding condition (current less than 50 ma), then the qihpc shows a resistive connection from d x to s x . d x and s x are the drain and source of the integrated dmos- transistor of channel x. the resistance value (dmos-r on ) is typically 1.4 w with a total tolerance of about +/- 0.35 w . c c delphi-lc peb 20570 pcm highway c-bus c-bus sign. ram ram iom iom a a -2 -2 test unit q-ihpc peb 2426 1 2 3 4 quad-u peb 2491
peb 2426 pef 2426 preliminary data sheet 10 06.99 ? figure 3 system integration ? u k0 channel1 ac-path channel 1 ovp1 u k0 channel2 ac-path channel 2 ovp2 u k0 channel3 ac-path channel 3 ovp3 u k0 channel4 ac-path channel 4 ovp4 v dd v dd v dd v ilf v dd gnd d 2 d 4 v ilf s 1 . . . s 4 c s1 . . . c s4 rd in1 . . . rd in8 rd out1 . . . rd out8 qihpc 4 * 2 w v dd pf 2 pf 1 pf 4 pf 3 nack 1 nack 2 nack 3 nack 4 v ilf d 1 d 3 v ilf r s1..4 4 * 220 nf c s1..4 r f rf pos rf neg 1700 w
peb 2426 pef 2426 preliminary data sheet 11 06.99 2 pin descriptions 2.1 pin configuration (top view) figure 4 pin configuration rfpos rfneg gnd pf1 pf3 pf2 nack1 pf4 nack2 nack3 nack4 cs3 d3 gnd s3 cs4 rdin5 gnd s4 d4 rdin6 rdin7 rdout3 rdin4 rdout4 rdout5 rdout7 rdout2 vdd rdout1 rdout6 rdout8 rdin8 rdin3 rdin2 rdin1 gnd s1 d1 cs2 cs1 s2 d2 vilf
peb 2426 pef 2426 preliminary data sheet 12 06.99 2.2 pin definitions and functions ? table 1 pin definitions and functions pin no. symbol input (i) output (o) function 28 v dd supply positive supply voltage, referred to gnd. operating voltage range from 3.0 v to 6.0 v. 3 12 19 37 gnd supply ground 44 v ilf supply isdn line feed voltage, referred to gnd. operating voltage range from -130 v to -30 v. 38 43 13 18 d 1 d 2 d 3 d 4 o drain connections of the output transistors of channels 1..4. these pins have to be connected (via external resistors) to isdn lines a (ring) of channels 1..4. 1 2 rf pos rf neg o current limitation of channels 1..4. these pins have to be connected to an external resistor r f . r f and r s1..4 are defining the output current limit for all four lines. 39 42 14 17 s 1 s 2 s 3 s 4 o overcurrent indication threshold. these pins have to be connected via external resistors r s1..4 to v ilf defining the overcurrent indication threshold of each line individually. 40 41 15 16 c s1 c s2 c s3 c s4 o external capacitors defining t oc -delays of channels 1..4. these pins have to be connected via external capacitors to v ilf defining the overcurrent indication delay. 4 5 6 7 pf 1 pf 2 pf 3 pf 4 i power feed signal of channels 1..4. logic high on pf 1..4 switches on the power feeding to the line of channel 1..4. 8 9 10 11 nack 1 nack 2 nack 3 nack 4 o not acknowledged signal of channels 1..4. logic low on nack 1..4 signals that either the isdn line of channel 1..4 is powered and in a normal power on condition or that power feed is not requested..
peb 2426 pef 2426 preliminary data sheet 13 06.99 36 35 34 33 20 21 22 23 rd in1 rd in2 rd in3 rd in4 rd in5 rd in6 rd in7 rd in8 i switch-on-signal of relay-channels 1..8. logic high on r in1..8 switches on the relay driver npn- transistor of channel 1..8. 29 30 31 32 27 26 25 24 rd out1 rd out2 rd out3 rd out4 rd out5 rd out6 rd out7 rd out8 o open collector output of relay-channels 1..8. when the relay driver npn-transistor of channel 1..8 is switched on, than this pin sinks a current of up to 40 ma. an integrated zener diode guards the qihpc against inductive voltage peaks from the relay coil. table 1 pin definitions and functions (continued) pin no. symbol input (i) output (o) function
peb 2426 pef 2426 preliminary data sheet 14 06.99 3 functional description 3.1 functional block diagram ? figure 5 functional block diagram junction temperature control bandgap biasing v dd 4 * 10 m a - + 1 m a r substrat - + 100 mv +/-10% substrat dmos d pd d ps zd gs t uf t f op f op dc r dc line current control v ilf c s1..4 s 1..4 d 1..4 logic nack 1..4 pf 1..4 20 m a 20 m a 2 k w 9.3 v relay drivers rd out1..8 rd in1..8 20 m a gnd line feed control 10..100 mv +/-20% rf pos rf neg
peb 2426 pef 2426 preliminary data sheet 15 06.99 in the functional block diagram, figure 5 , we can see four different types of circuit blocks: one biasing circuit, four line feed control circuits, four line current control circuits and eight relay driver circuits. 3.2 biasing circuit the bandgap circuit generates a constant voltage with respect to gnd. this reference voltage is converted into a current of about 20 m a which is necessary for level shifting. this current is converted back into 100 mv and 10..100 mv (depending on the value of the external resistor r f ) reference voltages with respect to v ilf . these reference voltages and the external resistors connected between pins s 1..4 and v ilf defines the line current limit and the overcurrent indication threshold. currents of about 10 m a are used for level shifting the power feed information. in the biasing block also all other biasing currents used on the chip are generated. intelligent junction temperature control in coordination with line current limiting protects the qihpc against overloads. also a fault condition on one line shall under no circumstance disturb a connection on another line. therefore a junction temperature control circuit is necessary. the junction temperature of the qihpc will be monitored by an integrated thermal detector with three threshold levels, as defined in table 2 power on requests will only be executed if the junction temperature is below t j1 (typical 130 c) and if no other line is in overcurrent condition. if the device junction temperature reaches the second threshold t j2 (typical 170 c), then all the line drivers in the current- table 2 thermal detector threshold levels symbol parameter description test conditions limits unit min typ max t j1 130 c thermal detector threshold guaranteed by design 120 130 140 c t h1 130 c thermal detector hysteresis guaranteed by design 10 c t j2 170 c thermal detector threshold guaranteed by design 160 170 180 c t h2 170 c thermal detector hysteresis guaranteed by design 10 c t j3 190 c thermal detector threshold guaranteed by design 180 190 200 c t h3 190 c thermal detector hysteresis guaranteed by design 10 c
peb 2426 pef 2426 preliminary data sheet 16 06.99 overload condition will be switched off by the qihpc. if the device junction temperature then still continues to increase to t j3 (typical 190 c), all the line drivers will be turned off by the qihpc. the line(s) in current overload will be switched off sufficiently fast once the second threshold t j2 is reached, i.e. before the t j3 threshold is reached. this guarantees a disturbance free operation on lines not affected by a fault condition. once a line had been switched off the relevant pf-pin has to be set to low and subsequently to high, for attempting to power this line again. the internal protection mechanisms (current limiting and junction temperature control) already provide full protection of the d 1..4 outputs against short circuits to a voltage between gnd and v ilf . note: the thermal protection mechanism of the qihpc is a protection against instant damages due to overload at the outputs. continuous high temperatures during operation, however, will reduce the life time of the qihpc. measures have to be taken to switch off the qihpc in case of a short-circuit. e.g. if pin nack x indicates an current overload condition, the qihpc should be deactivated after few seconds using pin pf x . 3.3 line feed control circuit the qihpc can supply the power for up to four transmission lines simultaneously. the exchange of activation commands and status information with the qihpc will occur via a parallel interface, consisting of one input (pf) and one output (nack) per line. the power switch can be controlled (pf) for each line individually. the status information (nack) can be monitored for each line separately. integrated pull-down current-sinks are connected to the input pins pf 1..4 . if one of these pins is not connected externally, the logic level at this pin is 0. logic level 0 means that the voltage on this pin is about 0 and logic level 1 means that the voltage level on this pin is about v dd . a diagnostic of possible fault conditions is available on the status information pins (nack) for each line separately. the nack pin is set to 1 when pf=1 and: - current on the line reaches the overcurrent indication threshold for longer than t oc . - over temperature (t j > t j3 ) is detected. - power feed setting is not acknowledged by the qihpc. see also table 3 .
peb 2426 pef 2426 preliminary data sheet 17 06.99 in case of simultaneous power up requests (pf 1..4 ) the qihpc take care of a proper start-up sequencing. the four channels have different priority. first priority for channel 1, second priority for channel 2 etc. by simultaneous power up requests on more than one channel, the channel with the highest priority will be powered first and only, and will normally start with current limiting condition. when this channel is powered up and the drawn current drops below the current indication level, the next channel will be powered. and so on (see also figure 6 and table 3). 3.4 line current control circuit two different current limiting circuits are integrated to control the dmos power switch. an ultrafast and a fast current limiting circuit. see also figure 5 . the ultrafast current limiting circuit consists of a bipolar npn-transistor t uf . note that bipolar npn-transistors are the fastest devices from the used technology. if the voltage between s 1..4 and v ilf exceeds about 0.7 v the dmos is switched off as fast as possible. table 3 function table for controlling one line pf current (other channels) current (this channel) t j nack comment 0 dont care dont care dont care 0 line feeding not requested at least one above indication threshold dont care dont care 1 power feeding not acknowledged and the line is not powered as long as an other line is in overcurrent condition dont care dont care > t j1 1 power feeding not acknowledged and the line is not powered, as long as the junction temperature is to high 1 dont care above indication threshold < t j2 1 feeding: this line is in over current condition 1 dont care below indication threshold < t j3 0 normal line feeding 1 dont care dont care > t j3 1 overtemperature condition, feeding is switched off 01 ? 01 ?
peb 2426 pef 2426 preliminary data sheet 18 06.99 0.7 v divided by r s1..4 = 2 w results in an ultrafast current limiting level of about 350 ma. this level has a strong tempera ture dependence (-40 c junction temperature gives about 420 ma and +120 c results in about 300 ma). the ultrafast current limiting circuit protects the qihpc against short circuit on the line side with a resulting current rising as fast as 2 a/100 nsec. the fast current limiting circuit keeps the voltage between s 1..4 and v ilf below a programmable voltage level. this results in a current limitation. zener diode zd gs protects the dmos-gate. diodes d pd and d ps are the parasitic drain-bulk-diode and drain-substrate-diode of the dmos transistor (junction isolated technology). the diodes do not provide overvoltage protection, negative surges would pass through to s 1..4 and v ilf affecting the battery voltage. extra overvoltage protection circuitry is necessary to conduct voltage surges form the line to ground, and to prevent that any current can flow into diodes d pd and d ps . typical value of dmos-on-resistance including internal wiring-resistance to the pins d 1..4 and s 1..4 is 1.4 w . to identify overcurrent, the voltage between s 1..4 and v ilf is compared to 100 mv. if the voltage exceeds this level, this is indicated to the line current control circuits. a resistor and the external capacitor c s define a lowpass filter (time delay) to suppress the changes on nack due to short overcurrent surges. this enables to filter the effects of longitudinal ac current. an external capacitor with a value of about 220 nf results in a delay time (t oc ) of about 25 msec. 3.5 relays driver circuit the output transistor is a bipolar npn. the maximal collector current should not exceed 40 ma. when switching off an inductive load, zener diode and npn clamps the voltage level on pin rd out1..8 at about 10 v. the 2 k w resistor limits the input current on pin rd in1..8 and additionally the npn collector current. if a pin rd in1..8 is not connected, the integrated pull-down current-sink holds the respective relay driver in switched-off condition.
peb 2426 pef 2426 preliminary data sheet 19 06.99 4 application hints 4.1 resistor r s1..4 the value of this resistor defines the overcurrent indication level. note, that the value of this resistor must be considered for line symmetry. the typical overcurrent indication level i ind can be programmed by using the following formula. ? 4.2 resistor r f the values of resistors r f and r s1..4 define the current limiting level. the typical overcurrent limitation level i lim can be programmed by using the following formula. ? 4.3 capacitor c s1..4 the value of this capacitor define the resulting delay time t oc for the overcurrent indication. for typical values of t oc as a function of c s1..4 see figure 6 . ? figure 6 delay time t oc as a function of the value of c s1..4 (typical values) i ind 100mv r s1 ? 4 ------------------- = i lim 100mv r f 20 m a + r s1 ? 4 ---------------------------------------------------- = 0 20 40 60 80 100 120 140 160 22 33 47 68 100 220 330 470 680 1000 c s1..4 [nf] t oc1..4 [msec]
peb 2426 pef 2426 preliminary data sheet 20 06.99 4.4 protection circuitry ? figure 7 proposal for a protection circuitry an external circuitry is needed to protect the qihpc against damages due to high voltages from the line. high voltages can be caused by lightning surges or foreign voltage contact. capacitor c and resistors r la and r lb are used to filter noise from the battery voltage v ilf , and reduces mismatches of the input resistance for ac-signals. r 2 mirrors the resistive path to the qihpc at wire, i.e. the resistance of d-mos and r s1..4 . these resistors and capacitor c shall provide compatibility with the requirements for longitudinal balance. the diode d 2 clamps a high positive voltage surge to gnd. the thyristor th conducts negative surges to gnd. th has to fire fast enough before high negative voltage could damage the qihpc or overload the voltage supply of v ilf . shorting voltage surges to gnd is sensed by the qihpc equivalent to a short-circuit at the line. it will react according to the programmed overcurrent indication and overcurrent limitation. gnd c line b line a hybrid of the u-transceiver r lb r la vilf d 2 th gnd to sink lightning current 0v r 1 i 1 i 2 d 1 r s1..4 r 2 s 1..4 d 1..4 qihpc peb 2426
peb 2426 pef 2426 preliminary data sheet 21 06.99 5 operational description the qihpc is compliant to the etsi ts 102 080 dynamic power feeding requirements using the lt power test load (see figure 8 ). there is no requirement for the order of powering up the lines, or for dependencies of controlling between the lines. ? figure 8 circuit with lt power source test loads with the lt power source test load from ts 102 080 the qihpc can power up four u line interfaces within about 2 seconds quasi simultaneous. the input sequence and expected output sequence with power dissipation diagram is shown in figure 9 . the power dissipation in the chip is quite small. a fault condition (short circuit) on one line does not affect the power up of the other lines. example: assumed a short circuit on line 3. a simultaneous power up request is applied to the qihpc. the power up of lines 1 and 2 will proceed as expected. when powering up line 3, the chip temperature control (t j2 ) will switch off this line. lines 1 and 2 are still powered and remain in normal power on condition. when the junction temperature is decreased to t j1 the qihpc will try to power up line 4. if there is no fault condition on line 4 the lines 1, 2 and 4 are finally in a normal power on condition. line 3 is still in power off. to to repeat the trial to powering up line 3, the input signal pf 3 must set to 0 and 1 again. v dd v dd gnd d 2 d 4 v ilf rd in1 . . . rd in8 rd out1 . . . rd out8 qihpc v dd pf 2 pf 1 pf 4 pf 3 nack 1 nack 2 nack 3 nack 4 v ilf d 1 d 3 channel1 1 k 400 m f 3 k channel2 1 k 400 m f 3 k channel3 1 k 400 m f 3 k channel4 1 k 400 m f 3 k v ilf s 1 . . . s 4 c s1 . . . c s4 4 * 2 w v ilf r s1..4 4 * 220 nf c s1..4 r f rf pos rf neg 1700 w
peb 2426 pef 2426 preliminary data sheet 22 06.99 ? figure 9 simultaneous power up sequence t t t t i d1 t 67 ma t i d2 t t t t t t 67 ma i d3 67 ma i d4 67 ma 0.5 sec 1.0 sec 1.5 sec 2.0 sec pf 1 pf 2 pf 3 nack 2 pf 4 nack 1 nack 3 nack 4 t power dissipation on chip 2 w 1 w 0.5 sec 1.0 sec 1.5 sec 2.0 sec 0
peb 2426 pef 2426 preliminary data sheet 23 06.99 6 electrical characteristics ? note: stresses above those listed here may cause permanent damage to the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. maximum ratings are absolute ratings; exceeding only one of these values may cause irreversible damage to the integrated circuit. 6.1 absolute maximum ratings parameter symbol limit values unit operating ambient temperature range:peb pef t a t a 0 to 70 - 40 to 85 c c storage temperature range t stg - 65 to 125 c voltage on pin v dd with respect to ground v ddmax - 0.4 to + 8 v voltage on pin v ilf with respect to ground v ilfmax - 140 to v dd + 0.4 v voltages on pins d 1..4 with respect to v ilf v d1..4max - 0.4 to + 150 v voltages on pins d 1..4 with respect to v ilf with series resistor r s = 5 w /figure 15 v d1..4maxrs - 3 to + 150 v pulse voltages on pins d 1..4 with respect to v ilf with series resistor r s = 5 w /figure 15: t = 200 msec / f = 50 hz or t = 50 msec / f = 16.7 hz v d1..4pulse - 3 to + 150 v p impulse voltages on pins d 1..4 with respect to v ilf with series resistor r s = 5 w /figure 15: t dur = 20 m sec / t rise = 25 nsec / non repetitive v d1..4impulse - 5 to + 160 v p voltages on pins s 1..4 with respect to v ilf v s1..4max - 0.4 to + 8 v voltages on pins d 1..4 with respect to voltages on pins s 1..4 v ds1..4max - 0.4 to + 140 v voltages on pins c s1..4 with respect to v ilf v cs1..4max - 0.4 to + 8 v voltages on pins pf 1..4 with respect to ground v pf1..4max - 0.4 to v dd + 0.4 v voltages on pins nack 1..4 with respect to ground v na1..4max - 0.4 to v dd + 0.4 v voltages on pins r in1..4 with respect to ground v ri1..4max - 0.4 to v dd + 0.4 v voltages on pins r out1..4 with respect to ground v ro1..4max - 0.4 to v dd + 0.4 v esd-voltage, all pins (human body model) v esd-hbm - 1 to + 1 kv
peb 2426 pef 2426 preliminary data sheet 24 06.99 ? note: in the operating range the functions given in the circuit description are fulfilled. ? 6.4 ac/dc-characteristics general test conditions: r s1..4 =2 w 0.1 % c s1..4 =220 nf 1 %(63 v) r f = 1700 w 0.1 % supply voltages for typical characteristics: v dd =5 v 1 % v ilf = - 100 v 1 % note: the listed characteristics are ensured over the operating range of the integrated circuit. typical characteristics specify mean values expected over the production spread. if not otherwise specified, typical characteristics apply at t a = 25 c and the given supply voltage 6.2 operating range parameter symbol limit values unit v dd supply voltage v dd + 3.0 to + 6.0 v v ilf supply voltage v ilf - 130 to - 30 v 6.3 static thermal resistance parameter symbol limit values unit junction to ambient r th, ja < 62.9 k/w junction to case r th, jc < 14.6 k/w
peb 2426 pef 2426 preliminary data sheet 25 06.99 ?. table 4 dc characteristics no. parameter symbol limit values unit test condition test fig. min. typ. max. supply currents 1 v dd current i dd 0.7 1.5 ma 10 2 v ilf current i ilf 0.4 1 ma excluding line currents 10 line currents, delay time t oc and dmos-r on resistance 3 overcurrent indication level i maxoc1..4 45 50 55 ma pf 1..4 = 1 11 4 current limiting level i max1..4 59 67 75.5 ma pf 1..4 = 1 11 5 line current in off-condition i maxoff1..4 010 m apf 1..4 = 0 11 6 delay time t oc t oc1..4 10 25 40 msec pf 1..4 = 1, i line >= 55 ma 11 7 dmos-r on resistance r on1..4 peb2426 1.05 1.4 1.75 w pf 1..4 = 1, i line = 25 ma 12 r on1..4 pef2426 0.8 1.4 2.0 w pf 1..4 , logic input levels 8 1 - input voltage v hpf1..4 2v 13 9 0 - input voltage v lpf1..4 0.8 v 13 10 pull down input current i pf1..4 10 20 30 m a0.8 v < v pf1..4 < v dd 13 nack 1..4 , logic output levels 11 1 - output voltage v hnack1..4 v dd - 0.4 v i source1..4 = 100 m a13 12 0 - output voltage v lnack1..4 0.4 v i sink1..4 = 100 m a13
peb 2426 pef 2426 preliminary data sheet 26 06.99 6.5 testing the electrical parameters ? figure 10 supply currents rd in1..8 , relay driver inputs 13 on - input voltage v on,rdin1..8 2.0 v dd v14 14 off - input voltage v off,rdin1..8 0.4 v 14 15 pull down input current i pd,rdin1..8 20 30 m a0 < v rdin1..8 < 0.4 v 14 rd out1..8 , relay driver outputs 16 saturation voltage v sat1,rd1..8 0.25 0.4 v v rdin1..8 = 2,4 v, i rdout1..8 = 33 ma 14 17 saturation voltage v sat2,rd1..8 0.20.40,5v v rdin1..8 = 2,4 v, i rdout1..8 = 40 ma 14 18 current in off- condition i off,rd1..8 020 m a v rdin1..8 = 0.4 v 14 table 4 dc characteristics (continued) no. parameter symbol limit values unit test condition test fig. min. typ. max. v dd v dd gnd d 2 d 4 v ilf rd in1 . . . rd in8 rd out1 . . . rd out8 qihpc pf 2 pf 1 pf 4 pf 3 nack 1 nack 2 nack 3 nack 4 v ilf d 1 d 3 pf 1..4 : all combinations rd in1..8 : open nack 1..4 : open rd out1..8 : open d 1..4 : open i dd i ilf s 1 . . . s 4 c s1 . . . c s4 4 * 2 w r s1..4 4 * 220 nf c s1..4 r f rf pos rf neg 1700 w
peb 2426 pef 2426 preliminary data sheet 27 06.99 ? figure 11 line currents and delay time t oc ? figure 12 dmos-r on resistance v dd v dd gnd d 2 d 4 v ilf rd in1 . . . rd in8 rd out1 . . . rd out8 qihpc v dd pf 2 pf 1 pf 4 pf 3 nack 1 nack 2 nack 3 nack 4 v ilf d 1 d 3 rd in1..8 : open nack 1..4 : open rd out1..8 : open channel2 gnd i maxoc2 i max2 i maxoff2 i line channel1 gnd i maxoc1 i max1 i maxoff1 i line channel3 gnd i maxoc3 i max3 i maxoff3 i line channel4 i maxoc4 i max4 i maxoff4 i line off ==> on: i maxoc1 , i max1 on: i maxoff1 off ==> on: t oc1 timer start stop t oc1..4 i line >= 55 ma off ==> on: i maxoc2 , i max2 on: i maxoff2 off ==> on: t oc2 off ==> on: i maxoc3 , i max3 on: i maxoff3 off ==> on: t oc3 off ==> on: i maxoc4 , i max4 on: i maxoff4 off ==> on: t oc4 v ilf s 1 . . . s 4 c s1 . . . c s4 4 * 2 w v ilf r s1..4 4 * 220 nf c s1..4 r f rf pos rf neg 1700 w v dd v dd gnd d 2 d 4 v ilf rd in1 . . . rd in8 rd out1 . . . rd out8 qihpc v dd pf 2 pf 1 pf 4 pf 3 nack 1 nack 2 nack 3 nack 4 v ilf d 1 d 3 rd in1..8 : open nack 1..4 : open rd out1..8 : open v ilf s 1 . . . s 4 c s1 . . . c s4 4 * 2 w v ilf r s1..4 4 * 220 nf c s1..4 r f rf pos rf neg 1700 w i ds1 = 25 ma gnd i ds2 = 25 ma gnd i ds3 = 25 ma gnd i ds4 = 25 ma gnd v ds1 v ds2 v ds3 v ds4 4 4 4 ds ds on i v r = 1 1 1 ds ds on i v r = 2 2 2 ds ds on i v r = 3 3 3 ds ds on i v r =
peb 2426 pef 2426 preliminary data sheet 28 06.99 ? figure 13 pf 1..4 , logic input levels and nack 1..4 , logic output levels v dd v dd gnd d 2 d 4 v ilf rd in1 . . . rd in8 rd out1 . . . rd out8 qihpc 4 * 1 k w pf 2 pf 1 pf 4 pf 3 nack 1 nack 2 nack 3 nack 4 v ilf d 1 d 3 r load1..4 rd in1..8 : open rd out1..8 : open i pf1 v hpf1 v lpf1 v pf1 i pf2 v hpf2 v lpf2 v pf2 i pf3 v hpf3 v lpf3 v pf3 i pf4 v hpf4 v lpf4 v pf4 i source1 v dd v hnack1 v lnack1 i sink1 i source3 v dd v hnack3 v lnack3 i sink3 i source2 v dd v hnack2 v lnack2 i sink2 i source4 v dd v hnack4 v lnack4 i sink4 v ilf s 1 . . . s 4 c s1 . . . c s4 4 * 2 w v ilf r s1..4 4 * 220 nf c s1..4 r f rf pos rf neg 1700 w
peb 2426 pef 2426 preliminary data sheet 29 06.99 ? figure 14 rd in1..8 , relay driver inputs and rd out1..8 relay driver outputs ? figure 15 test circuit for maximum dc-voltages, pulse voltages and impulse voltages on pins d 1..4 v dd v dd gnd d 2 d 4 v ilf rd in1 . . . rd in8 rd out1 . . . rd out8 qihpc pf 2 pf 1 pf 4 pf 3 nack 1 nack 2 nack 3 nack 4 v ilf d 1 d 3 nack 1..4 : open d 1..4 : open pf 1..4 : open i pd,rdin1 v on,rdin1 v off,rdin1 v rdin1 i pd,rdin2 v on,rdin2 v off,rdin2 v rdin2 i pd,rdin8 v on,rdin8 v off,rdin8 v rdin8 v dd v sat,rd8 i rdout8 i off,rd8 180 v dd i off,rd8 v sat,rd8 v dd v sat,rd1 i rdout1 i off,rd1 180 v dd i off,rd1 v sat,rd1 v ilf s 1 . . . s 4 c s1 . . . c s4 4 * 2 w v ilf r s1..4 4 * 220 nf c s1..4 r f rf pos rf neg 1700 w v dd v dd gnd d 2 d 4 v ilf rd in1 . . . rd in8 rd out1 . . . rd out8 qihpc v dd pf 2 pf 1 pf 4 pf 3 nack 1 nack 2 nack 3 nack 4 v ilf d 1 d 3 rd in1..8 : open nack 1..4 : open rd out1..8 : open pf 1..4 : all combinations v d4maxrs v d4pulse v d4impulse v ilf 5 w r s v d3maxrs v d3pulse v d3impulse v ilf 5 w r s v d2maxrs v d2pulse v d2impulse v ilf 5 w r s v d1maxrs v d1pulse v d1impulse v ilf 5 w r s v ilf s 1 . . . s 4 c s1 . . . c s4 4 * 2 w v ilf r s1..4 4 * 220 nf c s1..4 r f rf pos rf neg 1700 w
peb 2426 pef 2426 preliminary data sheet 30 06.99 7 package outlines ? p-mqfp-44 (plastic metric quad flat package) sorts of packing package outlines for tubes, trays etc. are contained in our dimensions in mm smd = surface mounted device

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